gui dao jiao tong she bei zhong fpga xin pian deng xiao xing yan zheng fang fa
Author(s): CHEN Guang, ZHENG Guiyan, LIU Weichao
Pages: 72-76
Year: 2016 Issue: 1
Journal: Railway Signalling & Communication Engineering
Keyword: equivalence checking; FPGA veriifcation; Formality; Conformal LEC;
Abstract: Veriifcation of the FPGA netlist generated by Synthesis or Place & Route has great importance for ensuring the design reliability. The post-synthesis simulation method widely used now has two major problems. One is the complexity with a long process, the other is the test coverage deifciency. The paper puts forward a verification method using equivalence checking and presents the verification process of FPGAs from majority manufacturers and the false treatment solutions. Comparing with post-synthesis simulation method, the equivalence checking method has lower cost and higher test coverage and would beneift greatly the design reliability.
Pages: 72-76
Year: 2016 Issue: 1
Journal: Railway Signalling & Communication Engineering
Keyword: equivalence checking; FPGA veriifcation; Formality; Conformal LEC;
Abstract: Veriifcation of the FPGA netlist generated by Synthesis or Place & Route has great importance for ensuring the design reliability. The post-synthesis simulation method widely used now has two major problems. One is the complexity with a long process, the other is the test coverage deifciency. The paper puts forward a verification method using equivalence checking and presents the verification process of FPGAs from majority manufacturers and the false treatment solutions. Comparing with post-synthesis simulation method, the equivalence checking method has lower cost and higher test coverage and would beneift greatly the design reliability.
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