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The Logic Synthesis Flow for ePro System
Author(s): 
Pages: 63-65
Year: Issue:  2
Journal: Beijing Electronics

Keyword:  时序约束 门级网表 综合;
Abstract: 本文以ePro系统为例,使用Synopsys公司的Design Compiler(DC)工具进行逻辑综合,介绍了综合所需的各种时序约束。
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