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A PowerPC High Performance Processing Unit Design with Fault-tolerant and Error-detectable SDRAM
Pages: 46-51
Year: Issue:  5
Journal: AEROSPACE CONTROL

Keyword:  PowerPC嵌入式计算机SDRAM容错检错;
Abstract: 介绍一款PowerPC架构的高性能嵌入式处理单元设计.利用PowerPC体系结构内建的差错检测和报告机制,采用CPLD设计和实现了三模冗余(TMR)SDRAM存储器模块,不但提供高速存储器的容错能力,还具有差错检测能力,提高了处理单元的可靠性.介绍一个分布式容错计算机的实例,并分析了该方案的优点.
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