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The Implementation of Cyclic Redundancy Check Code System Based on FPGA
Author(s): 
Pages: 12-14,31
Year: Issue:  6
Journal: Electronics Quality

Keyword:  Digital communicationsCyclic redundancy check code;
Abstract: Generating error problem during transmission systems for digital communication signal is pro-posed based on FPGA cyclic redundancy check code system.The use of hardware description language VHDL design implementation and verification process of generating cyclic redundancy check code gener-ated by the verification and simulation software for the hardware platform QuartusII CRC,complete the de-sign of the entire calibration system through test:The system improves communication quality,shorten the design cycle and reduce the error rate in the communication to ensure the correctness and completeness of the data,and improve the reliability of data communication,there is a certain value in engineering.
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