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Research of ParaIIeI Hardware Architecture for Matrix TrianguIarization Decomposition Based on ReconfigurabIe Computing System
Pages: 1642-1650
Year: Issue:  8
Journal: Acta Electronica Sinica

Keyword:  matrix triangularization decompositiontriangularization processparallel algorithmLU decompositionfield programmable gate array;
Abstract: The reconfigurable computing system became an important choice according to accelerating compute-intensive ap-plications.Among most compute-intensive applications,the matrix triangularization decomposition always was in the central position of research subjects and presented a great value to solve linear equation systems and matrix eigenvalue problems in science or engi-neering area.This paper analyzed the linear computing process of triangularization and proposed a hardware-adaptive parallel sub-matrix identity updating algorithm and a high-performance parallel structure hardware template for matrix triangularization on FPGA (Field Programmable Gate Array)according to the common triangularization computing process of the matrix triangularization de-composition.The research focused on the high-performance FPGA parallel structure implementation and optimization methods for the LU matrix triangularization decomposition.In theoretical analysis,the proposed algorithm presents better pipeline-parallelism and da-ta-parallelism during the matrix triangularization process.The experimental result shows that the proposed structure gets over decuple speedup compared to general-purpose processors and the previous works in vital performance.
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