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Designing an A/D Sampling Controller with CPLD/FPGA
Author(s): 
Pages: 37-38,64
Year: Issue:  2
Journal: ELECTRONIC ENGINEER

Keyword:  CPLD/FPGA采样控制器ADC0809VHDL语言有限状态机;
Abstract: 利用CPLD/FPGA目标器件设计一个采样控制器,按照正确的时序直接控制ADC0809的工作,完成二至十进制的转换并显示采样值.所有这些功能都采用VHDL语言进行描述.
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