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Design of a Time-to- Digital Converter for ADPLL Application
Author(s): GAO Yuan-pei, LI Wei, State Key Laboratory of ASIC & System, Fudan University
Pages: 168-
174+183
Year: 2015
Issue:
2
Journal: Journal of Fudan University(Natural Science)
Keyword: time-to-digital converter; vernier gated-ring-oscillator; all-digital phase-locked loop;
Abstract: A Time-to-Digital Converter(TDC)for All-Digital Phase-Locked Loop(ADPLL)application is designed.The TDC has two operation modes,coarse mode and fine mode.To enlarge the detectable range of fine mode,the TDC utilizes 1-bit decision-select structure and Vernier GRO as its two-stage Quantization Unit.Using a new structure comparator in Vernier GRO eliminates the limitation to detectable range when using SR flip-flop as comparator,and also improve the design flexibility of GRO delay cell.The TDC is designed in TSMC 0.13μm CMOS technology.With 1.2Vpower supply and 40 MHz sampling rate,simulation result shows that detectable range of coarse mode can be 25 ns,effective resolution and detectable range of fine mode is 30 ps,1.8ns.
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