The server is under maintenance between 08:00 to 12:00 (GMT+08:00), and please visit later.
We apologize for any inconvenience caused
Login  | Sign Up  |  Oriprobe Inc. Feed
China/Asia On Demand
Journal Articles
Laws/Policies/Regulations
Companies/Products
Bookmark and Share
Effect of Discrete Period on All-Digital Full-Hardware Phase-Locked Loop Using in Servo System
Author(s): 
Pages: 153-160
Year: Issue:  9
Journal: Transactions of China Electrotechnical Society

Keyword:  Phase locked loopall-digitalfull-hardwareservo systemfield-programmable gate array;
Abstract: The digital control system based on field-programmable gate array(FPGA) or application specific integrated circuits(ASIC) has the advantages of full-hardware, parallelism, and flexibility, so it is a high-speed, high-performance solution of magnetic encoder-to-digital converter(MEDC) with phaselocked loop(PLL). But there are some problems such as determination of parameters-region, optimization of word-length etc, which have a close connection with discrete period. The delta operator is employed to discrete the continuous-time PLL system so as to do the stability analysis of discrete-time PLL system with one-step-delay firstly, so the integer word-length of coefficients are determined. And then, error source model and error propagations model based on L2-norm are established, and the effect of discrete period on fractional word-length of improved PLL is analysed, so the design method of fractional word-length is derived. The simulation and experimental results verify the correctness and effectiveness of proposed analysis.
Related Articles
No related articles found