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The Design Example of Verilog HDL and Its Simulation & Synthesis
Author(s): 
Pages: 19-22
Year: Issue:  12
Journal: ELECTRONIC ENGINEER

Keyword:  Verilog HDL电子设计自动化数字电子系统系统仿真逻辑综合;
Abstract: 介绍了Verilog HDL的特点;讨论了EDA技术的设计思路;针对数字电子系统,用Verilog HDL设计了一个篮球30秒计时器,并在Cadence和Synopsys环境下成功地进行了仿真和逻辑综合.
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