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ji cheng dian lu
Pages: 64-66
Year: Issue:  8
Journal: Electronic Products China

Keyword:  低相位噪声锁相环基础设施收发器无线基站芯片组模数和数模转换时钟合成器智能电表射频卡;
Abstract: <正>无线基站射频卡低噪声计时芯片组8V19N4xx芯片组包括了JESD204B相兼容的灵活的射频锁相环(RF PLL)和时钟合成器,能满足2G、3G和4GLTE无线基础设施中高频率和低相位噪声的需求。通过采用IDT已被验证的FemtoClock NG技术,这种低相位噪声特性可使系统的模数和数模转换器(ADCs/DACs)实现高精度和低失真
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