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A Novel Interpolator Controlling Scheme in High-Speed Digital Timing Recovery Loop
Author(s): LIU Wang, ZHU Jiang, FU Yong-ming, XI Zhi-peng
Pages: 1-
5
Year: 2013
Issue:
10
Journal: Communications Technology
Keyword: gardner timing; interpolator controller; parallel structure;
Abstract: Timing recovery is one of the core parts for full-digital receivers,its processing speed is a re-straint to the maximum processing speed of the receiver. Based on conventional Gardner timing recovery, a modified timing recovery method involved a parallel controller in the high speed digital receivers is pro-posed. The modified controller can be used to provide interpolated phase for the interpolator to realize the interpolation function and decrease the system's sampling clock via parallel scheme at the same time. With 8psk signals as an example, this configuration is simulated and verified, indicating that the proposed inter-polator controller is a good solution to timing recovery, and effective for increasing data rate in timing loop, and thus can be used to implement fairly high incoming data.
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