The server is under maintenance between 08:00 to 12:00 (GMT+08:00), and please visit
later.
We apologize for any inconvenience caused
Design on Data Plane of Programmable Hardware-Based Virtual Router
Author(s): LIU Zhong-jin, LI Yong, YANG Mao, SU Li, JIN De-peng, ZENG Lie-guang
Pages: 1268-
1272
Year: 2013
Issue:
7
Journal: Acta Electronica Sinica
Keyword: virtualization; data plane; parallel pipeline; programmable hardware;
Abstract: Building virtualized network experiment platform is considered to be an effective method for network architecture innovation and validation .The structure and performance of the virtual router determines the capacity and flexibility of network ex-periment platform .In this article ,the virtual router′s data-plane architecture with parallel pipelines is presented .Combined with par-allel packet classification and asynchronous pointer polling scheduling mechanisms ,we implement isolated heterogeneous router in-stances on the same physical underlying .Prototype system is deployed on programmable hardware which is tested with software routers in real network environment .Experimental results show that compared with traditional single-pipeline architecture ,our design get greater flexibility and parallelism and supports heterogeneous router instances operating independently ;logic resources overhead and delay characteristics are not significantly increased while each router instance achieves wire-speed forwarding which is compara-ble with that hardware .
Citations
No citation found