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A variable step length frequency locked method of baseband signal clock extraction
Pages: 752-754
Year: Issue:  4
Journal: Journal of Southwest University for Nationalities(Natrual Science Edition)

Keyword:  锁频锁相环变频分频器基带信号时钟;
Abstract: 串行数字通信系统需要从一个串行数据流中抽取一个采样时钟.这个抽取通常由一个叫时钟及数据恢复单元的非线性电路实现,该电路负责跟踪信号中的低频相位变化.本文提出了一种从频率上跟踪、锁定基带信号发端时钟频率从而提取出基带信号时钟的方案.此方法比传统的锁相环提取时钟具有更好的性能.由于它适于采用硬件语言描述,因而可集成在各类数字芯片中.
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