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Design of a 32-bit Divider Based on FPGA
Author(s): 
Pages: 26-28
Year: Issue:  3
Journal: Electronic Engineer

Abstract: 介绍了一种使用可编程逻辑器件FPGA和VHDL语言实现32位除法器的设计方法.该除法器不仅可以实现有符号数运算,也可以实现无符号数的运算.除法器采用节省FPGA逻辑资源的时序方式设计,主要由移位、比较和减法三种操作构成.由于优化了程序结构,因此程序浅显易懂,算法简单,不需要分层次分模块进行.并使用Altera公司的QuartusⅡ软件对该除法器进行编译、仿真,得到了完全正确的结果.
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