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Research and Design of CMOS Charge Pump PLL PFD
Author(s): 
Pages: 551-556
Year: Issue:  9
Journal: MICRONANOELECTRONIC TECHNOLOGY

Keyword:  鉴频鉴相器锁相环死区D触发器锁存器;
Abstract: 介绍了鉴频鉴相器(PFD)在其发展过程中产生的结构,并对每一种结构的优缺点进行了比较.通过对原有PFD电路结构进行重新设计,在传统D触发器PFD的基础上提出了两种新型PFD:传输门D触发器型PFD和基于锁存器的PFD.电路设计基于TSMC公司的0.18μmCMOS工艺,仿真环境为Candence Spectre,仿真结果显示电路可以工作在2 GHz以上频率的应用环境下.相对于传统的PFD,新型PFD工作频率高、几乎无死区,而且具有噪声低、速度快的优点,在高速、低抖动、低噪声PLL中将有广泛的应用前景.
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