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Implementation of Convolution Code Encoder and Viterbi Decoder Based on FPGA
Author(s): 
Pages: 21-24
Year: Issue:  8
Journal: ELECTRONIC ENGINEER

Keyword:  卷积编码Viterbi算法FPGA寄存器交换法;
Abstract: Viterbi译码是对卷积码的一种最大似然译码算法.主要介绍卷积码的Viterbi译码器的FPGA(现场可编程门阵列)实现方案.根据卷积码的特点,设计了用寄存器交换法存储幸存路径的模块,充分利用FPGA触发器资源丰富的优点.同时,为使系统在保持同等性能条件下可以高效率实现,对Viterbi译码实现中的数据溢出和输出判决部分进行了优化,处理的结果使得系统的性能和效率都有提高.本设计已基于FPGA实现,译码速度快、延时小.
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