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Design of high speed interface between embedded system and DSP
Author(s): 
Pages: 36-37
Year: Issue:  4
Journal: ELECTRONIC MEASUREMENT TECHNOLOGY

Keyword:  S3C4510b高速缓冲存储器先入先出存储器嵌入式系统;
Abstract: 在嵌入式微处理器对FIFO进行读取操作时,由于一些微处理器本身自带高速缓冲存储器(Cache),会造成读数错误,本文将分析错误原因并给出3种解决此类错误的方案.在编写FIFO接口程序时,可以通过对Cahce进行刷新、禁用或反复赋新地址的方法予以解决.采用以上方法均可以使微处理器从FIFO读出期望的数据,从而降低系统的错误率,提高系统的可靠性.
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