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Implementation of speed match between DSP and peripheral chips using CPLD
Author(s): 
Pages: 73-75
Year: Issue:  4
Journal: ELECTRONIC MEASUREMENT TECHNOLOGY

Keyword:  速度匹配CPLDDSP;
Abstract: 在某些工业仪表与自动化装置中,数字信号处理器经常需要与不同速度的外设芯片进行接口.在TMS320Cxx等系列DSP芯片中提供了两种机制实现与外设芯片的速度匹配:一是利用软件设置DSP内部的等待状态控制寄存器,可插入0~7个机器等待周期;二是提供READY信号管脚,由外部电路控制可以产生任意数目的等待周期.本文应用CPLD分别采用图形输入法和VHDL语言编程产生等待信号,实现了DSP与外设芯片的速度匹配,简化了DSP访问外设时由软件产生等待的程序编写,提高了整个系统的执行速度.
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